Vinodkumar Khyamade
Senior Verification Engineer at Analog Devices
- Role
- Senior Design Verification Engineer at Analog Devices
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Vinodkumar Khyamade
Top-performing ASIC Verification engineer, Gained experience in verification of sub-system, Creating Verification plan, UVM test bench development, I have technical programming languages i.e System verilog, verilog, perl & Have knowledge of protocols like SPI, UART, I2C,I3C, APB and AHB.
Experience
Senior Design Verification Engineer
Mar 2022 — Present · Bengaluru, IN
Education
P D A College of Engineering, GULBARGA
Bachelor of Engineering - BE, Electronics and Communications Engineering
2010 — 2014
Siddaganga Institute of Technology (SIT), Tumkur
Master of Technology - MTech, signal processing
2014 — 2016
Skills
- Universal Verification Methodology (Uvm)
- Verilog
- Static Timing Analysis
- System Verilog
- Rtl Design and Test Bench Coding
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