Vinod Murshilli
Analog layout engineer
- Role
- Analog Layout Design Engineer at Synopsys Inc
- Location
- Pune, MH, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Vinod Murshilli
Hands-on experience on 180nm and INTEL 3nm* Having knowledge of Reliability issues like Electromigration, Latch-up, Antenna effect and Paracitics.* Team work experience.*Worked in 3-different projects which all are of lower node.*Two of them are completed from scratch.*Handled a complete CBB from the scratch.
Experience
Analog Layout Design Engineer
Nov 2024 — Present · Pune, IN
Education
Visvesvaraya Technological University
Bachelor of Engineering - BE
2017 — 2020
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.