Vinod Chityala

About Vinod Chityala

ASIC IP | SoC | uArchitecure | RTL design15+ years of experience in micro architecture design, ASIC IP & SoC RTL design and system level designs- HDL : Verilog, VHDL, SV- ASIC tools : VCS, ncsim, QuestaSim, LINT, SpyGlassLP, QCDC, LEC, ECO FLow, Design Compiler, Primetime - Protocols : PCIe, sATA, USB, MIPI (M-PHY, D-PHY, CSI-2, DSI), Gigabit Ethernet, 10G, DDR2/3, AXI, AHB, APB, SPI- SerDes / High Speed transceivers, Low Power Designs, STA/ Timing Closure, broad bring up- Cryptography / Security : AES, XTS-AES, GCM/GMAC- FPGA tool flows : Xilinx, Microsemi- Scripting : TCL, shell

Experience

1. Senior Asic Rtl Design Engineer

   Google

   Jan 2026 — Present · Bengaluru, IN

Education

• THE INSTITUTION OF ENGINEERS(INDIA)

  Bachelor of Engineering (BE)

Skills

• Amba Ahb
• Ddr2
• Serial Ata (Sata)
• Axi
• Serdes
• Verilog
• Mipi
• Apb
• Spyglass
• Vhdl
• Lint
• Ddr3
• High Speed Interfaces
• Digital Signal Processing
• Ethernet
• Xilinx Tools
• Questa Cdc
• Pcie
• Static Timing Analysis
• Questasim
• Cdc