Vineet Sharma

About Vineet Sharma

18+ years of experience in Front End IP/SoC design.• IP/RTL architecture & design, SoC architecture & integration with Mixed Signal IPs. • Exposure to low power as well as high speed designs.• Handled Boot, Debug/Trace, Security, pin-muxing, Clocking/Reset of SoCs. • Bus protocols: AXI, AHB, APB.• Lead teams in IP design and verification, SoC integration, ASIC quality checks (LINT/CDC/CLP), STA reviews and ECOs.• Cross functional Collaboration with: Verification, Validation, DFT, Analog/IO, Back-End/PD, Modeling, Emulation (FPGA/Palladium), Systems/Architecture, Firmware, Test & Chaz teams.• Managed and Lead teams of 15-20 engineers at different levels of experience.• Industry exposure: Storage/Flash, Video Codecs, Communication/Networking, Image Pipeline.• UFS, PCIe, Ethernet

Experience

1. Senior Technologist, Asic Design

   Sandisk

   May 2025 — Present · Bengaluru, IN

Education

• University of Minnesota

  Master of Science (M.S.), Electrical and Electronics Engineering (VLSI)

  2012 — 2013

• Dr B R Ambedkar National Institute of Technology, Jalandhar

  B.Tech

  2002 — 2006

Skills

• Xilinx Ise
• Board Development
• Lattice Isplever
• Modelsim
• Cadence Virtuoso
• Static Timing Analysis
• Cadence Virtuoso Layout Editor
• Synopsys Tools
• Cadence Schematic Capture
• Telecommunications
• Perl
• Verilog
• Synopsys Vcs
• C
• Vhdl
• Carrier Ethernet
• Soc
• Rtl Design
• Spice
• Fpga
• Asic
• Tetramax
• Microsoft Visual Studio C++
• Integrated Circuit Design
• Edk
• Dve
• Board Bring-Up
• Altera Quartus
• C++
• Ethernet
• Rtl Verification
• Functional Verification
• Hspice
• Cadence Nc-Verilog
• Xilinx
• Systemverilog
• Synopsys Design Vision
• Debugging