Vineeth Sai Padala

About Vineeth Sai Padala

I am a semiconductor professional with over 4 years of experience in the VLSI domain, specializing in ASIC Physical Design. My expertise spans advanced technology nodes of 7nm,5nm & 3nm.I possess a strong foundation in CMOS technology and digital electronics, complemented by in-depth knowledge of physical design methodologies and sign-off processes. I have been actively involved in all major stages of the physical design flow, including->Synthesis, Floorplanning, Power Planning, Placement, Clock Tree Synthesis (CTS), Routing, and Signal Integrity analysis, addressing cross-talk, electromigration (EM), and antenna effects->Low Power Design, with practical experience in implementing On-Off blocks, Multi-Voltage domains, and associated verification methodologies->Static Timing Analysis (STA), including timing ECOs, and metal ECO implementations->Physical Verification, with hands-on experience in DRC, LVS, IR drop and EM analysis, antenna fixes, and closure of all sign-off metrics->I have a knowledge of scripting language TCL and Unix.

Experience

1. Senior Physical Design Engineer

   MosChip®

   Oct 2025 — Present · Hyderabad, IN

Education

• Audisankara College of Engineering & Technology(Autonomous)

  Bachelor of Technology - BTech, Electrical and Electronics Engineering

  2017 — 2020

• Audisankara College of Engineering & Technology(Autonomous)

  Diploma, Electrical and Electronics Engineering