Vineeth Kumar Andavarapu
Design Verification Engineer at ChipSil Technologies
- Role
- Design Verification Engineer at Chipsil Technologies Pvt Ltd
- Location
- Hyderabad, IN
- LinkedIn followers
- 500 followers
About Vineeth Kumar Andavarapu
VLSI Design & Verification Engineer → A Highly motivated and detail-oriented professional seeking a challenging position in desired industry to leverage my expertise in RTL Design and Verification. → As an Electronics engineer, wanted to pursue my career in semi-conductor Industry where I can get an opportunity to grow as professional engineer and develop the skills that can contribute to the company\'s growth as well as enhance my knowledge by exploring new things. Here is a Sneak Peak of What I know - Digital Design. Verilog. System Verilog. RTL Coding. Universal Verification Methodology(UVM). Hands On Experience - → AMBA AHB to APB Bridge Verification. → Router 1x3 Design using Verilog & Verification using UVM. Behavioural Skills - Zeal to Learn New Things. Willingness to take new challenges. Self Motivated & Confident.
Experience
Design Verification Engineer
Dec 2024 — Present · Hyderabad, IN
Education
SSC From Govt High School, Visakhapatnam
Board of Secondary Education , 10th Class
Chaitanya Engineering College, Chaitanya Valley, Kommadi, Madhurawada,Pin-530041(CC-L6)
Diploma of Education, Electronics and communication Engineering
Chaitanya Engineering College
Bachelor of Technology, Electronics and communication engineering
2016 — 2019
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