Vineet Rathish

WORK HISTORY

EDUCATION

ABOUT VINEET RATHISH

I recently graduated with a Master’s degree in Electrical Engineering from San José State University, specializing in Digital Design and Verification. My academic journey and hands-on project experience have equipped me with a strong foundation in front-end VLSI design, RTL implementation, and ASIC/FPGA verification methodologies.I am passionate about building robust, scalable, and efficient digital systems. My core competencies lie in Verilog, SystemVerilog, and UVM, and I’m actively seeking opportunities in Front-End Digital Design and Verification roles including:> RTL Design Engineer> ASIC/SOC Design Engineer> Design/ASIC Verification Engineer> FPGA Verification Engineer> CPU/GPU/SOC Verification EngineerTechnical Proficiencies> HDLs/HVLs: Verilog, SystemVerilog, UVM> Verification Methodologies: UVM, Constrained Random Testing, Assertions, Coverage-Driven Verification, Scalable Testbench Design> Programming: C, C++, Python> Scripting: Python> Protocols: AMBA AXI4, APB, AHB, I2C, SPI, UART, PCIe, DDR> Design Concepts: FSMs, RTL Design & Synthesis, STA, CDC, MIPS Pipeline, Cache CoherencyI bring a combination of strong debugging skills, methodical verification strategies, and a deep understanding of digital logic fundamentals. I’m committed to continuous learning and excited to contribute to innovative and high-impact silicon development teams.