Vineet Nayak
- Role
- Senior Design Verification Engineer at 高通
- Location
- San Diego, CA, US
- LinkedIn followers
- 500 followers
About Vineet Nayak
Making Chips Secure.
Experience
Senior Design Verification Engineer
Nov 2021 — Present
HW security DV Making Chips Secure.
Education
Ravenshaw University
Associate of Science - AS, Science
2008 — 2010
Ira A. Fulton Schools of Engineering at Arizona State University
Master's degree, Electrical Engineering
2017 — 2019
S.c.b medical public school
ICSE
1998 — 2008
Odisha University of Technology and Research
Bachelor of Technology (B.Tech.), Electrical Engineering
2010 — 2014
Skills
- Microsoft Office
- Ni Multisim
- Cadence Icfb
- Embedded C
- Rtl Verification
- Microcontrollers
- Electronic Projects
- Arm Cortex-M3
- Embedded Systems
- Cadence Virtuoso
- Simulations
- Perl
- C
- Hspice
- Multisim
- Automation
- Systemverilog
- Robotics
- Programming
- Arm
- Rtl Coding
- Tcl-Tk
- Html
- Universal Verification Methodology (Uvm)
- Proteus Isis
- Modelsim
- Xilinx
- Arm Cortex M4
- Cadence Encounter
- Matlab
- Microsoft Excel
- Cadence Incisive
- Xilinx Vivado
- Arm Architecture
- Verilog
- Rtl Design
- Mips Assembly
- Arm7
- Cadence Virtuoso Layout Editor
- Simvision
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.