Vineet Dubey
Staff Engineer, ASIC Digital Design Verification Methodology at Synopsys | Ex-Intel
- Role
- Staff Engineer at 新思科技股份有限公司
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Vineet Dubey
I am passionate about VLSI design and verification. I have a hand on knowledge of RTL design, STA, Clock domain crossing, FPGA flow. also, created verification environment with SV Testbench for my master\'s final thesis. I have taken training in UVM.
Experience
Staff Engineer
Jul 2024 — Present · Bengaluru, IN
Education
Krishna Institute of Engineering and Technology,Ghaziabad
Bachelor of Technology (B.Tech.), Electronics and Communications Engineering
2012 — 2016
University of Hyderabad
Master of Technology (M.Tech.), INTEGRATED CIRCUIT TECHNOLOGIES
2016 — 2018
GLENHILL SCHOOL
INTERMEDIATE, Science
2009 — 2011
Skills
- Silvaco
- Powerpoint
- Microsoft Excel
- Gym
- Chipscope Pro
- Research
- Modelsim
- Matlab
- Vcs
- Field-Programmable Gate Arrays (Fpga)
- Vhdl
- Simulations
- Vcsmx
- Project Management
- Microsoft Office
- Originlab
- Xilinx Ise
- Verification and Validation (V&V)
- Embedded C
- Adventure Travel
- Agilent Ads
- Electronics
- Microsoft Word
- Leadership
- Verilog
- Management
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