Vineet Bhatnagar
DV Engineer at Meta
- Role
- Asic Engineer, Design Verification at Meta
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Vineet Bhatnagar
B.E.(Electronics & Communication) with 14+ years of experience in ASIC Verification domain.
Experience
Asic Engineer, Design Verification
Feb 2025 — Present · Bengaluru, IN
Education
Manipal Academy of Higher Education
Bachelor of Engineering (B.E.), Electrical, Electronics and Communications Engineering
2007 — 2011
Lucknow Public College
12th Standard, PCM
2005 — 2006
Lucknow Public Collegiate
High School
1992 — 2004
Skills
- Modelsim
- Soc Verification
- Debugging
- Verification
- Verification Plan
- System Verilog Assertions
- Ovm
- Vlsi
- Unix
- Open Verification Methodology
- Vhdl
- Simulations
- Code Coverage
- C
- Field-Programmable Gate Arrays (Fpga)
- Verilog
- Universal Verification Methodology
- Coverage Driven Verification
- Assertion Based Verification
- Rtl Verification
- Sv
- Ip Verification
- Fpga
- Asic
- Test Planning
- Uvm
- Ethernet
- Xilinx
- Systemverilog
- Functional Verification
- Embedded Systems
- Functional Coverage
- Universal Verification Methodology (Uvm)
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.