Vinay Mallik P.
DFT Design Engineer
- Role
- Dft Design Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Vinay Mallik P.
Responsible for Scan insertion, ATPG, Simulation, Synthesis and LEC • Knowledge on…
Experience
Dft Design Engineer
Apr 2022 — Present · Bengaluru, IN
Performed scan top-level simulations for Server SoCs to validate test architecture.Owned block-level scan implementation for multiple blocks, including scan chain trace, DRC analysis, and pattern simulation.Debugged and resolved scan DRC issues using SpyGlass DFT, ensuring clean handoff for synthesis and improved design testability.Developed and deployed the complete SoC DFT UPF flow, debugging and resolving VCLP errors.Defined isolation strategies for DFT components and collaborated with cross-functional teams to resolve UPF-related issues.
Education
Geethanjali English Medium High School
High School
2006 — 2007
Jawaharlal Nehru Technological University, Kakinada
Bachelor’s Degree, Electronics and Communication Engineering
2009 — 2013
Sri Chaitanya Junior Kalasala
Intermediate, MPC
2007 — 2009
Sree Vidyanikethan Engineering College
Master’s Degree, VLSI
2014 — 2016
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