Vinay Bharbhari

Emulation Engineer, Cerebras Systems

Role
Sr Member of Technical Staff at Cerebras
Location
Santa Clara, CA, US
LinkedIn followers
500 followers
Information TechnologyView LinkedIn profile

About Vinay Bharbhari

Graduated from San Jose state university, MSEESpecialization in ASIC/SoC Design and Verification.Summary Currently working as Fullchip SoC design verification engineer at Intel FPGA group (Altera). 5 years of IP/SoC verification and emulation experience along with 3 years of ASIC RTL design experience. Bring up X1 SoC on Veloce emulation platform was one of the notable contributions at Flex-Logix. Team player, self-motivated and passionate individual with experience in adapting to start-up culture quickly. Current visa status: H1B work authorization and I-140 approved.Technical skill setKey skills: SoC/IP pre-silicon verification, Emulation on Veloce platform, Constraint Random verification, Universal Verification Methodology (UVM), SV Assertions, Coverage-driven verification, ASIC RTL design, STA, GLS SDF verification, FPGA verification, customer support IP integration, Low-power UPF verification, Verilog-AMS verification.Programming Language: Verilog, System Verilog, UVM, Python, C, Shell/Bash scripting.Tools: Mentor Questa Sim, Veloce and Visualizer, Synopsys VCS, Verdi and Synplify Pro, Cadence Xcelium.Protocols: AMBA AXI, AHB, APB, JTAG, I2C, SPI.

Experience

  1. Sr Member of Technical Staff

    Cerebras

    Jul 2024 — Present · US

Education

  • Visvesvaraya Technological University

    Bachelor's degree, Electrical, Electronics and Communications Engineering

    2008 — 2012

  • St Marys high school

    High School

    1995 — 2006

  • San José State University

    Master's degree, Digital VLSI

    2014 — 2016

Skills

  • Systemverilog
  • C
  • Programming
  • Xilinx Ise
  • C++
  • Rtl Design
  • Soc
  • Vhdl
  • Simulations
  • System on a Chip (Soc)
  • Field-Programmable Gate Arrays (Fpga)
  • Matlab
  • Application-Specific Integrated Circuits (Asic)
  • Core Java
  • Testing
  • Cadence
  • Cadence Virtuoso
  • Ic
  • Java
  • Universal Verification Methodology (Uvm)
  • Perl
  • Embedded Systems
  • Static Timing Analysis
  • Digital Electronics
  • Microcontrollers
  • Circuit Design
  • Cmos
  • Integrated Circuits (Ic)
  • Integrated Circuit Design
  • Very-Large-Scale Integration (Vlsi)
  • Computer Architecture
  • Linux
  • Modelsim
  • Verilog
  • Microsoft Office
  • Vlsi
  • Fpga
  • Asic

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Vinay Bharbhari — Sr Member of Technical Staff at Cerebras in Santa Clara, CA, US | Unifers