Vinayaka Bhat
Principal Engineer - IO PAD Layout at Microchip Technology Inc.
- Role
- Principal Engineer at Microchip Technology Inc.
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Vinayaka Bhat
Core Competencies:* IO Library development consisting of various IO interfaces -GPIO, LVCMOS, I2C, SLIMBUS, DDR IO* Experience in IO layout design in higher nodes. Worked on lower nodes as well.* IO ring development for Inline, Core limited, PAD arrangement.* Comprehensive understanding of Architecture cells and its requirements.* Knowledge about Power bus.* In-depth knowledge of reliability issues like ESD, Latch up and good understanding ofEM and Antenna issues.* Experience in EM checks and Al, Cu Packaging checks.
Experience
Principal Engineer
Mar 2025 — Present
Education
BNM Institute Of Technology
Bachelor of Engineering - BE, Electronics and communication
Skills
- I/O Layout Design
- Verilog
- 16nm Finfet Technology
- Cadence Virtuoso
- Vlsi
- Shell Scripting
- Vhdl
- Rtl Design
- Lvs
- Drc, Dfm Cleanup
- Usb3.0
- Ncsim
- Analog Layout
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