Vinayak Musle
R&D Synopsys | Design Verification | UVM | SV
- Role
- Staff Engineer at 新思科技股份有限公司
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Vinayak Musle
Verification Engineer with a Master\'s degree in VLSI Design from National Institute of Technology with 3 years experience in the semiconductor industry in IP and SoC verification. Hands on experience with PCIe, SATA, AMBA AXI, and APB protocols. Worked on VIP development, assertions, coverage and testcases and debugging design. Proficient in System Verilog and Universal Verification Methodology(UVM).* Experience in IP, subsystem verification and SOC integration. Knowledge of Digital electronics, Verilog,* System Verilog and UVM.* Methodologies: UVM* Scripting Language: Perl* IDE Tools: Synopsys Verdi, VCS, Mentor Questasim* Version control: Perforce and CVS* Operating System:Linux and WindowsContact: v••••••••@gmail.com
Experience
Staff Engineer
Dec 2023 — Present · Bangalore Urban, IN
Education
Sushila Devi Bansal College of Technology (SDBCT)
Bachelor of Engineering - BE, Electrical, Electronics and Communications Engineering
National Institute of Technology, Kurukshetra, Haryana
Master of Technology, Very large scale intigration(VLSI)
2016 — 2018
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