Vinay Sreedhara

About Vinay Sreedhara

5+ Years of professional experience in the VLSI industry delivering high quality results for companies like Google, Meta(Reality labs) and Intel in the Department of Physical Design and Verification.Expertise : Standard Cell Schematic and layout automation, RTL Design, Synthesis, Physical Design tasks such as Floorplanning, Power Planning, Placement, CTS, STA, EM-IR, PPA-Optimization, Physical Verification(DRC, LVS, DFM, Antenna, Density, PERC), Runset Dev Validation (LVS, ERC), Current Density Analysis and Fixing, Computer Aided-Design(CAD).Design Interests : Microprocessor System Design, CPU, GPU, DDR, DPU Tools : DC/DCT(dc_shell), Genus, Fusion Compiler(FC), IC Compiler(ICC), Innovus, PrimeTime(PT/PTSI), Tempus, VCLP, Conformal, IC Validator(ICV), IC Validator WorkBench(ICVWB), Calibre, CalibreDRV, Cadence Virtuoso, Voltus, QuestaSimNodes worked on : 14A, 18A(Intel), 3ne, 4nm(TSMC), 5nm(Samsung), 7nm(Intel), 10nm(Intel), 14nm(Intel).Scripting/Coding Skills : Unix, System Verilog, Verilog, TCL, Shell, Python.

Experience

1. Silicon Engineer

   Meta

   Dec 2025 — Present · Austin, TX, US

Education

• Vidhyavardaka college of engineering

  Bachelor of Engineering

• NIIT Institute

  Programming in C

• NIIT Institute

  Object Oriented Programming using C++

• Portland State University

  Master of Science - MS

• RV-VLSI Design Center

  Advanced Diploma in ASIC Design

• Vidhyaashram PU College

  Science (PCME)