Vinay Kumar

About Vinay Kumar

Professional Summary An enthusiastic Physical Design & STA engineer with total experience of 5 years in implementation (PnR) and static timing analysis(STA). Currently working at SAMSUNG SEMICONDUCTOR INDIA R&D as Associate Staff Engineer. Had done total of 8 design tape outs from RTL to GDS11 implementation and 5 blocks tape outs in Timing Closure(STA). Experienced at handling complex CTS blocks with multiple clocks, spine CTS implementation and congested designs with 70% standard cell utilization. Handled blocks with 10 million gate count and 24 lanes of high speed SERDES interface and complex source synchronous timing paths. Key Skills Comprehensive knowledge of physical design implementation, physical design strategies, and static timing analysis. Excellent knowledge of ASIC design flow.(Synthesis, Floor Plan, Power Plan, Placement, CTS, Route, RC extraction, STA, Timing closure ) Good hands on experience in handling complex blocks of multi-million gates and achieving better PPA. Ability to pick up new flows, learn on the job and influence QOR. In-depth knowledge and good hands on of EDA tools.(INNOVUS, Design Compiler, PRIME TIME SI, IC Compiler) Familiar with scripting languages and good at automating scripts.(TCL, Perl, and UNIX ) Experienced in deep sub-micron design of process node 14nm,10nm and 5nm. Strong debug skills and automation savvy and good communication skills.

Experience

1. Senior Staff Engineer

   Samsung Semiconductor

   Mar 2024 — Present · Bengaluru, IN

Education

• National Institute of Technology Surat

  Bachelor of Technology (B.Tech.), Electrical, Electronics and Communications Engineering

  2012 — 2016