Vinay C.

About Vinay C.

With over 10 years of work experience in the semiconductor industry, I am a Principal Engineer at Intel Corporation, where I enable state of the art design solutions to improve power, performance, area and efficiency. I am passionate about collaborating across various domains and groups to align and improve structural design tools, flows, and methodologies, and to bring diverse perspectives and experiences to the team.In my current role, I have developed a comprehensive data analysis framework to efficiently track design execution and tool quality over the course of the project life cycle. I have also worked with internal and external foundry partners to enable the process node for Intel design requirements, and enabled multi-vendor TFM for synthesis to tape-in flows, resulting in significant improvement in design efficiency. Additionally, I have closely worked with EDA vendors to enable and influence the latest capabilities in the structural design domain. Previously, I was the structural design lead for a multi-die client SOC on multiple process nodes, where I was responsible for implementing low power design methodologies, and developing in-house placement and routing engines that reduced power consumption and improved routing quality. I also worked on post-silicon debug lab to identify, root-cause, and fix timing failures on silicon.

Experience

1. Distinguished Engineer

   Cadence

   Jan 2024 — Present

Education

• Purdue University

  Ph.D., Low Power VLSI

  2008 — 2013

• Indian Institute of Technology, Kharagpur

  Bachelor of Technology, Electrical Engineering

  2002 — 2006