Vinay Ashok Somanache

About Vinay Ashok Somanache

PROJECTS HANDLEDIn Cadence Invecas Current Role as Technical Director and SOC architect for AI SOC/Indian DefenseRelated VLSI SOCs/RISC-V processor SOC for TSMC 6nm/12nm/28nm Technologies Worked as Director/DMTS for IoT/ADAS-based platform SOC. Handling Design Team/verification team/DFT Team. Worked on Security IPs required for IoT (AES/PKA ECC/TRNG). Working as an architect and Handled Integration of USB3.2 Controllers /LPDDR4 controllers/PCI Gen3 Express Domain/Display Port/Peripheral protocols such SPI/QSPI/I2C/UART/I2S/PWM/ADC/WDT/RTC. Handled subsystem Design/Verification of USB3.2 Controllers /LPDDR4-5 controllers/PCI Gen3-4 Express.In Open-Silicon Working as Architect for next generation of High bandwidth Memory IPs (HBM controller IP and PHY IP). Worked for the Test platform for Artificial Intelligence Applications In Broadcom1 SATA Protocol Stack, Design & verification & 2 SAS4 Development 2. Design of SAS/SATA Link Layer. Hardware Architecture of Security IPs blocks, Architect of the Key Management Module, Data encryption blocks 4. Flash Media Controller worked as architect, Architecture & design of core 4. Hard Disk Controller, Architecture changes to the legacy controller to cater to the new technology of the Disk media.In Cisco Systems India Pvt limited1. MAC Role: Technical Contributor Architect & Design of MAC Transmit and Receive MAC for 10/40/100GIn Conexant Systems India Pvt limited1. Technical lead For AXI master core and Coded the same, highly configurable to cater multiple Applications 2. Involved in Verification flow and verification plan and Actively engaged in Driving the Verification activity using specman eVC.3. Technical Lead for the architecture of AXI based PCI Express Endpoint device. In Synopsys India Pvt limited1. Design and Verilog Coding of 5C Encryption/Decryption EngineIn Control net India Pvt Limited1. INFINIBAND PHY, LINK IP Role: Architect, Design, RTL coding, FPGA testing.• Architectural Design and Verilog coding for ASIC/FPGA implementation of Infiniband Digital Physical layer IP.• Design and Verilog coding of PCI-based Test Environment and PCI Core Interface glue logic.Specialties: IoT platforms, ADAS, Flash Technology, PCI Express 1.0 and 2.0, AMBA 2.0, SAS, SATA, Hard Disk Controllers

Experience

1. Distinguished Engineer

   Cadence

   Jan 2026 — Present

Education

• Goa University

  Bachelor of Engineering - BE, Electronics and telecommunication

  1996 — 2000