Vimarsh Srivastava
Principal Design Engineer at Cadence | Ex - Arm | BITS-Pilani
- Role
- Principal Design Engineer at Cadence
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Vimarsh Srivastava
Working in Memory Design Team at ARM, BangaloreSkills: Memory Architecture, Margining, Characterization, ATPG, Scan chainsTools : Cadence Virtuoso, Synopsys Custom Explorer, Mentor Tessent, Fastscan, Tetramax, Synopsys and Cadence Extraction toolsSimulators : Hspice, Finesim, Spectre, XPS, Hsim.Languages: Shell Scripting
Experience
Principal Design Engineer
Sep 2025 — Present · Bengaluru, IN
Education
Birla Institute of Technology and Science, Pilani
Engineer's Degree, MSc(Hons) Physics & BE(Hons) Electrical & Electronics
2010 — 2015
Skills
- Python
- Research
- Pspice
- Cadence Virtuoso
- Microsoft Office
- Comsol
- Fdtd
- C
- Programming
- Ltspice
- Synopsys Tools
- Microsoft Powerpoint
- Microsoft Word
- Simulations
- Microsoft Excel
- Perl Automation
- Originlab
- Autocad
- Matlab
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.