Vimal Mer Bharwad

About Vimal Mer Bharwad

As an ASIC Design Trainee Engineer at eInfochips, an Arrow company, I am passionate about designing and developing innovative and efficient solutions for the semiconductor industry. I have completed my training in Physical Design, where I learned to implement various algorithm-level designs using tools such as Intel Quartus Prime and Xilinx Vivado. During my research internship at Ganpat University, I worked on a novel Asynchronous FIFO design using Verilog. Over time, I’ve expanded my skills across the entire frontend design flow, including functional specification development, architecture, microarchitecture, RTL coding (Verilog/SystemVerilog), design documentation, simulation, linting, and synthesis. I’ve contributed to several real-world projects such as a Floating Point Unit with UART interface, AHB to APB Bridge, a complete UDP/IP controller using AXI-Stream and AXI-Lite, and an ADC interface for automotive applications. I have recently completed my M.Tech in VLSI System Design from Ganpat University under the Work Integrated Learning Program at eInfochips. This unique program allowed me to combine academic learning with practical exposure to real industry projects. In addition to core VLSI work, I’ve explored areas like Artificial Intelligence, Reverse Engineering, and Malware Analysis, earning multiple certifications through Udemy. I hold a strong foundation in Electronics and Communication, having completed my B.E. from Gujarat Technological University, Ahmedabad in 2022, where I was awarded the silver medal for securing 2nd rank in my batch. My goal is to become a best-in-class engineer with a deep understanding of the VLSI domain and its real-world applications.

Experience

1. Asic Fpga Rtl Design Engineer

   eInfochips (An Arrow Company)

   Aug 2024 — Present · Ahmedabad, IN

Education

• Gujarat Technological University, Ahmedbabd

  Bachelor of Engineering - BE

  2018 — 2022

• Ganpat University

  Master of Technology - MTech

  2022 — 2024