Vilas P Nakade

About Vilas P Nakade

A self-motivated, an action oriented visionary leader with 20+ years of experience in Semiconductor domain# Currently working as a techno manager, managing 40+ members team, leading emerging HBM & LPDDR projects simultaneously with FTE & contact employees located at multi geography# Hands-on experience in cutting-edge technologies like TSMC 3nm to 28nm, SS4, Intel18a, GF12, TI# Proficiency in full custom layout, AMS, RF layout, high speed layout, in-depth knowledge and hands-on experience on CMOS planner, FinFET, BiCMOS, FDSOI, GAAFET process# Skilled in area estimation, Shielding, Antenna, IO ring, seal ring, RC reduction, PPA optimization, DFM, Yield, abutment checks, reliability, matching techniques, cross talk, shielding, ESD, latch-up, PERC, clamp planning for IO PAD Ring and clusters, Package-On-Package, Die to Die interposer, HDMiM/SHDMiM Cap, EMIR & self-heating, Bump mapping, RDL/AP bump routing, FlipChip, Bond pad, seal ring integration, clock planning and optimization, yield enhancementsWorked and handled layout ownership of RF blocks (like LNA, BBF, Mixer), Analog macros (like TX/RX driver, ADC, SarADC, DAC, PGA, Amplifiers, PLL, TMON, RTC), Power management blocks (like Charge pump, LDO, Bandgap, voltage regulator, Buck-book converter), Audio codecs, ESD components, TCoil, inductor layout, high speed and slew control IOs, GPIO library,#Proficiency on LEF/DEF/GDS generation, DRC/LVS/ERC verifications, Density, DFM score, quality/reliability check. Advanced understanding of Antenna, DFM, EMIR, PERC, Layout editor tools like Synopsys custom compiler, Cadence Virtuoso XL, Verification: ICV, Calibre, Assura, PV, K2, PERCWorked with leading companies like Synopsys, AMD, Qualcomm, Intel, TI, SCL, Sasken, Wipro#Having strong debugging and problem-solving skills, delivering challenging projects, troubleshooting, yield enhancements#With innovation at my core, I harness agility, embrace change, overcome challenges with courage and resilience, self-driven, result oriented contributor#Received Team Award for outstanding delivery of a high-stakes project, meeting stringent customer requirements and tight deadlines. Earned multiple awards, spot bonuses & appreciation for first-pass silicon successes#Successfully built a layout team by hiring right talent, technical mentoring#Expertise in building high-performance teams, Seasoned mentor, cross-functional & global team collaboration, innovation, automation, quality improvement, process development, articulate strategies, risk mitigation, drive engagements

Experience

1. Sr Manager Layout Design

   新思科技股份有限公司

   Feb 2025 — Present · Bengaluru, IN

Education

• CDAC ( VLSI )

  PGD, VLSI

  2001 — 2001

• Chintamani High School, Kalamb, Dist-Yavatmal (SSC Board, Amaravati)

  SSC (10th)

  1988 — 1992

• Amravati University

  BE ( Electronics and Tel ), ( Electronics and Tel )

  1995 — 1998

• Jilha Parishad HighSchool, Sarul (Babhulgaon) , Dist-Yavatmal (MS)

  8th

  1989 — 1990

• Sikkim Manipal University

  MBA - Marketing, Marketing

  2010 — 2012

• Government Polytechnic, Amaravati (Maharashtra)

  Diploma ( Elect & Tel )

  1992 — 1995

Skills

• Cadence
• Ic
• Analog
• Silicon
• Mixed Signal
• Power Management
• Xilinx
• Semiconductors
• Drc
• Asic
• C
• Spice
• Soc
• Vhdl
• Simulations
• Modelsim
• Virtuoso
• Perl
• Eda
• Cadence Virtuoso
• Verilog