Vikrant Mehendale
SOC RTL Design Engineer at Intel Corporation
- Role
- Soc Rtl Integration Design Engineer at Intel
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
About Vikrant Mehendale
I am Vikrant Mehendale. I am pursuing my master\'s at Portland State University in Electrical Engineering in the field of Hardware Designing Verification and Validation. Currently I have 3+ years of experience in RTL design and integration. I am keen to explore more areas in RTL Design, Verification as well as Validation. My skills include,Languages: Verilog, System Verilog, C, Python.Applications: ModelSim, QuestaSim, Xilinx ISE, Pycharm.
Experience
Soc Rtl Integration Design Engineer
Oct 2021 — Present · Santa Clara, CA, US
Debug Fabric Design (DFD) designed and integrated at SoC level, collaborating with various teams for implementation.• Integrated and routed debug components according to floorplan, resolving functional and clock domain bugs,reset domain bugs.• Wrote RTL and Python codes for small/glue logic, enhancing automation.
Education
Mumbai University Mumbai
Bachelor of Engineering, Electrical, Electronics and Communications Engineering
2014 — 2018
Portland State University
Master's degree, Electrical and Computer Engineering
2019 — 2021
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