Vikram Deep

About Vikram Deep

21 yrs of experience in Design implementation and timing activities like CPU Timing, STA Sign-off, Constraints, Synthesis, Logic Equivalence, Physical Design and Standard Cell Library Development- 20+ successful tapeouts on nm technologies ranging from 4nm to 90nm on designs like Processors, MCU, RADAR, WiFi, BT, FM, GPS, BLE etc- Good experience of leading and working in cross-functional team cultures spanning across multiple Geo-locations like India, Israel, US and Europe- Very good understanding of SoC DFT Architecture, Clocking and Timing Sign Off flows- Developed methodology for constraints creation and verification flows for Sign off- Innovated various solutions to save tool runtimes, reduce licence cost and improve schedule timelines- Worked mostly on products catering to wireless devices like Mobiles, IoT & Automotive etc, especially in low power- Hands on experience across multiple EDA vendors tools- Strong academic background.Specialties:Timing Constraints Definition, Coding and VerificationStatic Timing Analysis (STA)Final Timing Sign offSynthesisFormal EquivalenceClock Tree ConstraintsTCL ScriptingTiming eco fixes and closureMentoring and Coaching

Experience

1. Cpu Physical Design Engineer

   Intel

   May 2022 — Present · Bengaluru, IN

Education

• Institute of Technology and Management, Gurgaon, Haryana, India

  B.E, Electronics and communication

  2000 — 2004

Skills

• Tcl
• Perl
• Physical Design
• Timing
• System on a Chip (Soc)
• Verilog
• Primetime
• Soc
• Asic
• Static Timing Analysis
• Dft
• Semiconductors
• Logic Synthesis