Vikas Gupta
RTL/FPGA design Engineer | NIT Hamirpur | ECE | VHDL | Verilog | Xilinx Vivado | PCIe Gen1-6 PHY layer | AXI | Ethernet | TCP/IP | QestaSim | CDC | STA | FIFO | FPGA design | Lint | IP creation & integration | Debugging
- Role
- R & d Engineer at Logic Fruit Technologies
- Location
- Gurugram, HR, IN
- LinkedIn followers
- 500 followers
About Vikas Gupta
As an R&D Engineer and NIT Hamirpur graduate with over 2.8 years of experience, I have worked on the RTL design and verification of high-speed protocols in Xilinx FPGA boards. My experience includes the PCIe Gen1-6 PHY layer, Ethernet, TCP/IP and AXI protocols.I have resolved complex CDC and timing violations, debugged designs in both simulation and hardware, and ported designs from one FPGA to another. I am proficient in the complete FPGA design flow, IP creation, IP integration, FIFO, Timing constraints and skilled in Verilog and VHDL.I have experience in Xilinx Vivado, QuestaSim, and Wireshark. My validation experience includes hardware debugging using ILA and VIO and signal integrity analysis using the Keysight M8070B software. Additionally, I have knowledge of Python, Perl, and Shell scripting languages for automation.
Experience
R & d Engineer
Apr 2024 — Present · Gurugram, IN
Education
National Institute of Technology Hamirpur-Alumni
Integrated MTech , Electronics and Communication Engineering
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