Vikas Gokhale

About Vikas Gokhale

Accomplished, customer-focused IC design engineering leader leveraging over 18 years of experience leading cross-functional, global teams in the development of complex system-on-a-chip (SoC) designs, from RTL to production silicon. Recognized as a strong and resourceful leader in building cohesive teams and partnering with cross functional business leaders to effectively manage and deliver on a multitude of ASIC/SoC design projects. Core competencies:Application-Specific Integrated Circuit (ASIC)/System-on-Chip (SoC)| Verilog/System Verilog Micro-architecture/Design | Project LeadershipSynthesis (Design Compiler)| STA (Prime Time)Formal Verification | Verification | FPGA prototypingProcessors (ARM, PowerPC, V850E)| Protocols/Standards (Networking, PCI-E, AXI, USB, DDR3/L/4) CAREER HIGHLIGHTS 10+ years of hands-on experience in Register Transfer Level (RTL) design and verification Ability to provide comprehensive design debug support (verification, FPGA emulation, silicon validation) Experience leading all aspects of complex system-on-a-chip (SoC) designs from micro-architecture, RTL, synthesis/STA to tape-out to production Experience with many complex SoC chips for AR/VR, Server, Data Center, Mobile Daomin, involving, DSPs, multi-core processors (ARM M0+, M33, A7, A9, R4, A52,A72, A53/PowerPC etc.) & Interface IPs, NoC, CCNs etc. Provided technical guidance & expertise in implementing efficient synthesis/STA methodology Strong problem solving, decision making and communication skills

Experience

1. Director, Design Engineering

   Socionext US

   Apr 2025 — Present · Milpitas, CA, US

Education

• Devi Ahilya Vishwavidyalaya

  B. E., Electronics and Instrumentation

  1989 — 1993

• Shree Dayanand Higher Secondary school, indore

  Higher Secondary 12th Grade, Mathematics & Science

  1985 — 1989

• Indian Institute of Technology, Kanpur

  M. Tech, Electrical Engg

  1995 — 1997

Skills

• Rtl Design
• Functional Verification
• Processors
• Tcl
• Pcie
• Rtl Coding
• Protocols(Pcie, Axi, Amba, Usb, Plb, Ddr)
• Integrated Circuit Design
• Testing
• Bus Models
• Amba Ahb
• Signal Integrity
• Perl
• Embedded Systems
• Eda
• Dft
• Verilog
• Technical Leadership
• Ic
• Logic Synthesis
• Micro-Architecture/Design
• Vlsi
• Physical Design
• Soc
• Xilinx
• Systemverilog
• Arm
• Semiconductors
• Static Timing Analysis
• Timing Closure
• Fpga
• Vhdl
• Simulations
• Asic
• Lint
• Formal Verification
• Debugging
• Silicon
• Linting
• Usb