Vikal Chandra
RTL Design Engineer | FPGA & ASIC | Image & Video Processing | Verilog, SystemVerilog | AXI, VDMA, DSP, High-Speed Design, DDR
- Role
- Rtl Design Engineer at 3rditech
- Location
- Delhi, IN
- LinkedIn followers
- 500 followers
About Vikal Chandra
Contact:+91••••••••55 | v••••••••@gmail.com Open for New Roles: RTL Design & Verification (ASIC/FPGA/SoC), FPGA Design, Emulation Notice Period: Immediate Joiner For Quick Discussion, Schedule a Meeting: https://calendar.app.google/uYapAedoHawb3bTNA Passionate RTL Design Engineer with 3+ years of experience in FPGA, ASIC, and Image Processing. Proficient in: Verilog, SystemVerilog, AXI, VDMA, DSP, CDC, STA, Lint, UVM, Vitis HLS, Vivado, Quartus Prime Expertise in: Image sensor integration, video pipelines, and protocol verification Experience with: DDR3 memory architecture and cache optimization Strong background in: RTL design, debugging, and high-speed digital design Successfully contributed to image processing, memory architecture optimization, and protocol development for leading semiconductor companies. Open to challenging opportunities in FPGA/ASIC design, RTL Verification, and SoC development. Let’s connect!
Experience
Rtl Design Engineer
Dec 2023 — Present · Delhi, IN
Education
National Institute of Technology Durgapur
Master of Technology - MTech
Lodi Kisan Inter College, Mahadevopur, Uttar Pradesh State Board
10th/SSC
Gurukula Kangri Vishwavidyalaya
B.Tech
Lodi Kisan Inter College, Mahadevopur, Uttar Pradesh State Board
12th/HSC
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