Vijendra Meshram
Lead Design Engineer
- Role
- Lead Design Engineer at Cadence
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Vijendra Meshram
9+ years of experience in analog layoutExperience in Analog IC Layout Design using - Intel_i18A, 5nm, 14nm, CMOS- 40nm, 55nm, 90nm, 130nm, 110nm and 180nm ProcessesWorked on Finfet 5nm(tsmc) projectProficient in custom analog/mixed-signal designLayout design on Cadence Virtuoso Layout Editor L/XLExperienced in floor planning, placement, power routing of blocksExperienced in problem solving skill for LVS/DRC errorsAbility to work efficiently
Experience
Lead Design Engineer
May 2024 — Present · Hyderabad, IN
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