Vijayeendra Vijay Rao
TPU Silicon Validation Engineer at Google
- Role
- Tpu Silicon Validation Engineer at Google
- Location
- Sunnyvale, CA, US
- LinkedIn followers
- 500 followers
About Vijayeendra Vijay Rao
Highly motivated and results-oriented Senior ASIC Test Engineer experienced in designing, developing, and executing test plans for complex ASIC products. Proven ability to bring up ASICs, perform functional and performance validation, and debug failures. Expertise in Python scripting for test automation, data analysis, and instrument control. Adept at collaborating with cross-functional teams, including design, verification, and software engineers, to ensure comprehensive test coverage and successful product delivery.Passionate about contributing to cutting-edge hardware development.Programming Languages: Python, MATLAB, VB.net, C, C++, Verilog, SystemVerilogASIC Testing: Bring-up, Validation, Debugging, Test Plan Development, Functional Testing, Performance Testing, CharacterizationTest Automation: Scripting, Instrument Control, Data Analysis, Report GenerationLab Instruments: Oscilloscope, Multimeter, AWG, Power supply, Temperature Controller, Spectrum Analyzer, Logic Analyzer.PCB Design: Cadence Capture CIS, PCB Editor
Experience
Tpu Silicon Validation Engineer
May 2025 — Present · Sunnyvale, CA, US
Education
Sri Jayachamarajendra College Of Engineering
Bachelor’s Degree, Instrumentation Technology and Engineering
2012 — 2016
The University of Texas at Dallas
Master’s Degree, Electrical, Electronics and Communications Engineering
2016 — 2018
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