Vijay Bhargava
Senior ASIC Design Engineer at Apple Inc.
- Role
- Senior Asic Design Engineer at Apple
- Location
- San Francisco, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Vijay Bhargava
Wide gamut of VLSI design experience ranging from frontend (rtl/integration/verification)…
Experience
Senior Asic Design Engineer
Jan 2016 — Present
Developing nextGen iProducts!
Education
Maharshi Dayanand University
B.E (E&C) with Honours, Electronics and Communication
1997 — 2001
Skills
- Low-Power Design
- Primetime
- Logic Synthesis
- Static Timing Analysis
- Timing Closure
- Amba Ahb
- Vlsi
- Verilog
- Integrated Circuit Design
- System on a Chip (Soc)
- Physical Design
- Rtl Coding
- Rtl Design
- Soc
- Asic
- Application-Specific Integrated Circuits (Asic)
- Digital Signal Processors
- Tcl
- Clock Tree Synthesis
- Systemverilog
- Functional Verification
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