Vijaya Rakesh
IC Design Engineer at Xilinx
- Role
- Ic Design Engineer at Xilinx
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Vijaya Rakesh
Specialties: Analog Mixed Signal Circuit Design and VerificationSERDES Analog I/O\'sSignal Integrity ChecksASIC Design and VerificationFIFO\'s Deisgn PCS VerificationLibrary generation to PrimeTime checks
Experience
Ic Design Engineer
Mar 2010 — Present
Education
Vignan University
B.Tech, Electronicd and Communication Engineering
2002 — 2006
Indian Institute of Technology, Madras
M.Tech., Microelectronics and VLSI Design
2007 — 2009
Skills
- Lvs
- Ic
- Static Timing Analysis
- Tcl
- Analog
- Semiconductors
- Verilog
- Soc
- Vhdl
- Eda
- Analog Design
- Low-Power Design
- Rtl Design
- Serdes
- Physical Design
- Cmos
- Rtl Coding
- Cadence Virtuoso
- Vlsi
- I/O
- Modelsim
- Primetime
- Timing Closure
- Functional Verification
- Fpga
- Asic
- Pll
- Digital Signal Processors
- Analog Circuit Design
- Drc
- Xilinx
- Systemverilog
- Mixed Signal
- Circuit Design
- Integrated Circuit Design
- Signal Integrity
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