Vijay Desai
Senior Manager (Physical Design/STA) at Marvell Semiconductor
- Role
- Senior Manager at Marvell Technology
- Location
- Pune, MH, IN
- LinkedIn followers
- 500 followers
About Vijay Desai
Hands on experience in 180/152nm, 90nm, 28nm and 16nm designs.• Experience in timing closure in PnR at block level.• Netlist to GDSII Implementation using Synopsys and Cadence tools- Hands on Floor planning, pin placement, Placement, CTS, Routing experience using Synopsys ICC and Cadence Encounter- Static IR Drop Analysis using Synopsys PrimeRail- Formal verification checks Synopsys formality- Good practice on fixing Physical violations (DRC, LVS, ERC, Antenna ).• Good knowledge of TCL, Ruby & Perl scripting.
Experience
Senior Manager
Sep 2025 — Present · Pune, IN
Education
Institute Of Technology, Nirma University
Bachelor of Technology (B.Tech.), Electronics and Communication Engineering
2009 — 2013
Skills
- C++
- Scripting
- Asic
- Vhdl
- Perl
- C
- Vlsi
- Physical Design
- Static Timing Analysis
- Digital Electronics
- Rtl Design
- Tcl
- Verilog
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