Vignesh U

About Vignesh U

Results-driven RTL Verification Engineer with over 4+ years of hands-on experience in pre-silicon verification, specializing in System Verilog and UVM-based methodologies. I have expertise in developing testbenches, simulation environments, and debugging designs across both IP and Test Chip-level projects. With a solid foundation in protocol verification, I’ve also made significant contributions to Test Chip verification by executing gate-level simulations and driving verification flows that replicate full SoC environments with focused partitions.My experience spans from initial test planning to functional coverage closure, consistently delivering high-quality, high-coverage verification results under tight schedules. I also have a basic understanding of scripting (Python and Perl) to automate and optimize workflows, improving efficiency throughout the verification cycle.My collaborative approach, attention to detail, and commitment to staying current with evolving verification tools and standards make me a valuable asset in dynamic, innovation-driven teams. I am passionate about solving complex design challenges and continuously refining verification strategies to ensure first-silicon success.

Experience

1. Hardware Verification Engineer

   IBM

   Feb 2026 — Present · Bengaluru, IN

Education

• Sri Narayana Guru School, Kudroli, Mangalore

  Tenth, High School/Secondary Diplomas and Certificates

  2014 — 2015

• St Joseph Engineering College, Mangaluru

  Bachelor of Engineering - BE, Electrical and Electronics Engineering

• Canara College

  Twelth, PCME

  2015 — 2017