Vignesh Radhakrishnan

About Vignesh Radhakrishnan

ASIC Design Engineer with 8+ years of experience in digital design and verification, currently at Apple. I specialize in low-power, high-performance RTL design and have contributed to various SOC subsystem designs from microarchitecture to silicon debug. Previously at Samsung, I worked on UVM-based verification for PCIe PHYs. I’m driven by a passion for efficient silicon design and thrive in cross-functional environments where precision meets innovation.

Experience

1. Asic Design Engineer

   Apple

   Jun 2020 — Present

   Designed and implemented RTL for high-performance, low-power subsystems.• Partnered with architects and cross-functional teams—including verification, implementation, DFT, and Silicon Validation—to drive the design from microarchitecture through synthesis, resolving complex timing and power challenges, and supporting silicon debug.• Validated RTL through comprehensive front-end design checks, including lint, CDC, RDC, and VCLP, ensuring robust and clean handoffs.• Collaborated with implementation teams to craft project-specific synthesis strategies, delivering high-quality netlists optimized for backend integration.• Worked closely with the DV team to develop and execute a rigorous verification plan, enabling early bug detection and resolution.• Delivered precise ECOs to address critical late-stage design issues, ensuring smooth tapeout with minimal risk.

Education

• The University of Texas at Austin

  Master of Science in Engineering, Electrical and Computer Engineering

• Anna University Chennai

  Bachelor of Engineering (BE), Electronics and Communications Engineering

Skills

• Data Structures
• Ltspice
• Microsoft Word
• Microsoft Excel
• Rtl Verification
• C++
• Arduino
• Universal Verification Methodology (Uvm)
• Digital Circuit Design
• Multisim
• Signal Processing
• System Verilog
• Matlab
• Verilog
• Pspice
• Vlsi
• Sql
• Sva