Vidyadhar Jambhale
Design Verification Engineer at Qualcomm
- Role
- Design Verification Engineer at Qualcomm
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Design Verification Engineer
Jul 2019 — Present · Bengaluru, IN
Education
Tilak Highschool,Karad
High School
2003 — 2008
Ramrao Adik Institute of Technology
Engineer’s Degree, Electronics and Telecommunication
2010 — 2014
Vellore Institute of Technology
Master’s Degree, VLSI Design
2015 — 2017
Skills
- Verilog
- Perl
- Embedded Systems
- Linux
- Modelsim
- Very-Large-Scale Integration (Vlsi)
- C++
- Tcl
- System on a Chip (Soc)
- Electronics
- Application-Specific Integrated Circuits (Asic)
- Debugging
- Customer Service
- Digital Ic Design
- Matlab
- Asic
- Rtl Verification
- Cadence Virtuoso
- Field-Programmable Gate Arrays (Fpga)
- C
- Vhdl
- Synopsys Tools
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