Vidyadhar Duvva
Physical Design Verification Engineer.
- Role
- Pd Engineer at Microsoft
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Vidyadhar Duvva
Physical Design Verification Engineer with 8+ years of experience in Physical Verification, full‑chip integration, advanced‑node layout development, and signoff closure across 2nm, 3nm, 10nm, 22nm, and 28nm technologies. My expertise spans on Packaging (flip_chip/wirebond), DRC/LVS/EM/IR, Antenna and latch‑up closure, PG mesh design, ESD structures, and custom routing. I work extensively with Synopsys and Cadence tools and build automation using Tcl/Tk and UNIX. I’ve contributed to complex SoCs at Microsoft, Intel, and Analog Devices, consistently delivering signoff‑clean designs. Passionate about semiconductors, deep debugging, and design automation, I enjoy solving hard problems and driving high‑quality silicon.
Experience
Pd Engineer
Jul 2023 — Present · Hyderabad, IN
Education
Sri Vaninikethan High School
ssc, Higher Education/Higher Education Administration
2007 — 2011
SR junior college
Intermediate, M.P.C
2011 — 2013
MALLAREDDY ENGINEERING COLLEGE
Bachelor of Technology (B.Tech.), E.C.E
2013 — 2017
Skills
- English
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