Vidya Govindan
Senior RTL Design Engineer at Microsoft
- Role
- Senior Rtl Design Engineer at Microsoft
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Vidya Govindan
Expertise in Digital design and RTL coding using HDL (Verilog/VHDL).Hands on Experience with FPGA’s (Xilinx,Altera and Lattice).Experience in creating test bench, simulation, emulation and debugging.Hands on experience with Signal generators, Oscilloscopes and Spectrum Analyzers.Good knowledge and experience on communication protocols (UART, SPI and I2C).Understanding requirements, identifying basic blocks and preparing design and verification documents.
Experience
Senior Rtl Design Engineer
Dec 2024 — Present
Education
Indian Institute of Technology, Madras
Short Term Course, DSP
2011
Indian Institute of Technology, Kharagpur
Master of Science - MS, Computer Science
2016 — 2019
Sandeepani School of VLSI Design and Verification
Professional Development Course in VLSI Design and Verification, VLSI
2011 — 2012
Cochin University of Science and Technology
Bachelor of Technology (B.Tech.), Electronics and Communications Engineering
2007 — 2011
Skills
- Lattice Diamond
- Planahead
- Rtl Design
- Altera Quartus
- Fpga
- Vlsi
- Testing
- Rtl Coding
- Modelsim
- Very-Large-Scale Integration (Vlsi)
- Xst
- Xilinx
- Systemverilog
- C++
- C
- Programming
- Vhdl
- Xilinx Ise
- Field-Programmable Gate Arrays (Fpga)
- Matlab
- Embedded Systems
- Verilog
- I2c
- Microcontrollers
- Spi
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