Vidhyanandhan Sathishkumar

About Vidhyanandhan Sathishkumar

I’m a graduate student in Electrical and Computer Engineering at the University of Wisconsin–Madison, specializing in Digital and ASIC Design with a strong focus on Low-power ASIC design, RTL development, CPU/GPU microarchitecture, and hardware accelerators.My work spans the full stack of hardware design—from microarchitecture and SystemVerilog RTL to physical design and tapeout. I’ve taken multiple designs through complete ASIC flows (RTL → synthesis → P&R → GDS → STA), including a CNN accelerator currently in tapeout prep using SKY130. I also have hands-on experience building complex systems like a pipelined RISC-V processor and FPGA-based control systems, with an emphasis on performance, power, and area optimization.Before grad school, I was part of the engineering team at CynLr, where I led electronics R&D for high-performance vision and robotics platforms. My work involved heterogeneous compute systems (Jetson + FPGA), high-speed design system-level Hardware engineering (PCIe Gen4, USB 3.2), real-time motion control, delivering significant improvements in latency, efficiency, and system performance.I’m particularly interested in roles involving ASIC design, microarchitecture, and hardware acceleration for AI/ML.Feel free to connect if you’d like to discuss digital design, ASIC flows, or opportunities in this space.

Experience

1. Design and Development - Product

   CynLr

   Aug 2022 — Present

Education

• University of Wisconsin-Madison

  Master of Science - MS, Electrical and Computer Engineering

• Amrita Vishwa Vidyapeetham

  Bachelor of Technology - BTech, Electronics and Instrumentation Engineering

  2018 — 2022