Vidhula Pallavor
SoC DV intern @Qualcomm | Master\'s @Cornell | Verilog, SystemVerilog, Scripting | Seeking full time roles from Jan 2026
- Role
- Soc Design Verification Intern at Qualcomm
- Location
- Ithaca, NY, US
- LinkedIn followers
- 500 followers
About Vidhula Pallavor
Master\'s in Engineering in Electrical and Computer Engineering at Cornell University, currently interning in Qualcomm\'s SoC DV team. Experienced in Python, Verilog, SystemVerilog, and C, with hands-on contributions through 3 internships and multiple academic projects. Seeking full-time opportunities in Design and Verification roles, starting Jan 2026.
Experience
Soc Design Verification Intern
Jun 2025 — Present · Hyderabad, IN
Developed Python tool to extract and compare runtime and session time arguments; enabled sub-3s differential analysis for 5K+ line logs using GUI-based diff viewer, aiding rapid regression debug. • Built a static analysis tool to cross-check ~500MB of RTL and testbench code in 15s, flagging registers not included in testbenches and outputting RTL trace paths to accelerate coverage gap identification.
Education
Vellore Institute of Technology
Bachelor's degree
2020 — 2024
Cornell University
Master's degree
2024 — 2025
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