Victor F Andrade

WORK HISTORY

EDUCATION

SKILLS

ABOUT VICTOR F ANDRADE

Proven technical leadership working with teams of highly skilled designers in the development of custom/semi-custom digital components, across many generations of AMD processors. Designs included memory arrays, SRAMs, ROMs, Register-File arrays and other custom specific IPs, including the base-cell components of compiled arrays.• Definition and scheduling of design milestones, supervising team activities across geographical sites, including assessment and write-up of performance reviews for members under supervision.• Background in digital design of custom circuits using static, dynamic styles, cell based synthesis, pseudo-place and timing driven place-route methods.• Developed functional verification flow written in PERL to prove equivalency between RTL and transistor behavior.• Expertise in the establishment of circuit guidelines to maximize yield margins, design integrity and robust operation, by defining minimum metrics for full coverage of functional, electrical, layout/DFM construction and reliability limits.• Tape-out checklists definition, review procedures/scheduling, monitoring AIs and closure till final approval for mask release. Developed web based flow for auto creation of reports and trend completion charts.• Experience in silicon debug, characterization and ECO procedures from initial silicon bring-up through successful production launch.• Design,technology and foundry teams liaison in the incorporation of design rules pertaining to the memory arrays and bit-cell transistor components, for many generations of SOI/bulk CMOS processes technologies leading up to 28nm geometries.• Experience in the development of test-chips and sub-components for the characterization of new process parameters and the design metrics critical for performance and power projections.