Vicky Chikhalekar
Principal Engineer @ Marvell Technology
- Role
- Principal Engineer at Marvell Technology
- Location
- Pune Division, MH, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Vicky Chikhalekar
Currently Principal Engineer at Marvell: 12+ Years in RTL Design, Expertise in Microarchitecture, Digital Design, CDC, and Synthesis, with an MTech in VLSI Design.
Experience
Principal Engineer
Nov 2024 — Present · Pune, IN
Education
Visvesvaraya National Institute of Technology
Master of Technology - MTech
2010 — 2012
Dr. Babasaheb Ambedkar Marathwada University, Aurangabad
Bachelor of Engineering - BE
2005 — 2009
Skills
- Application-Specific Integrated Circuits (Asic)
- Static Timing Analysis
- Digital Electronics
- C
- Verilog
- Logic Synthesis
- Clock Tree Synthesis
- Rtl Design
- Functional Verification
- Integrated Circuit Design
- Cmos
- Uvm
- System on a Chip (Soc)
- Physical Design
- Synopsys Primetime
- Xilinx
- Systemverilog
- Very-Large-Scale Integration (Vlsi)
- Fpga
- Asic
- Modelsim
- Place & Route
- Synopsys Design Compiler
- Matlab
- Vlsi
- Vhdl
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