Vicky Joseph
Senior RTL Design Engineer
- Role
- Senior Rtl Design Engineer at Meta
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Vicky Joseph
VLSI Design and Verification Engineer - has an interest to learn and to innovate new ideas. Equally open to working and sharing responsibility with a team. Possess capabilities of working with a team and alone->> Skills - Verilog HDL, FPGA, System Verilog, UVM, STA, C,C++ language including OOPS Concepts->> Area of interest - RTL/FPGA Design and Verification->> To work smart with full determination and dedication to achieve organizational as well as personal goals.
Experience
Senior Rtl Design Engineer
Feb 2025 — Present · Bengaluru, IN
ASIC chip design and verification for complex mathematics with deep netlist interconnections with layout design
Education
KNS Institute Of Technology
Bachelor of Engineering - BE, Electrical, Electronics and Communications Engineering
RBANMS PU College.
High School Diploma, PCMC
Maria Niketan High School
SSLC
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