Vicky Chavan

About Vicky Chavan

Experienced Design Verification Engineer with a demonstrated history of working in the service industry.Skilled in Debugging and well versed in Verilog,Object Oriented Programming,SystemVerilog,UVM and scripting.Have HandsOn experience on Verification of multiple SubSystem IP implementing layered protocols like PCIe(Gen1/2/3).Have developed Verification plan, environment architecture documents, test plan for IP SS Verification using system Verilog. Well versed with memory access protocols such as APB and AXI and experienced with the creation of directed and random testcase as per Vplan.Have experience in SOC LEVEL GLS (Functional simulation) simulation (7nm,10nm and 22nm).

Experience

1. Senior Design Verification Engineer

   Wipro

   Jan 2020 — Present · Pune, IN

   Working on validating Gate Level Netlist of an soc based project using DualSim GLS simulation.(7nm/10nm/22nm)• Responsible to Debug the simulation failures which caused due to X propogation, non resettable flops, and optimization of Netlist due to synthesis• Supported the junior team-mates to understand the working of DualSimGLS simulation• Task included the communication of the functional bugs found in the designs to the respective designers TOOL_USED- VERDI

Education

• Veermata Jijabai Technological Institute (VJTI)

  Bachelor of Technology - BTech

  2013 — 2017

Skills

• Electronics
• Matlab
• C++
• Core Java
• Project Management
• Microprocessor 8085&86
• Customer Service
• Microsoft Office
• Management
• Soldering
• 8051 Microcontroller