Vibha Lakshminarayana
Principal Design Engineer at Cadence Design Systems
- Role
- Principal Design Engineer at Cadence
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
About Vibha Lakshminarayana
I am a highly motivated and passionate engineer interested in computer architecture and VLSI design. A great team member and skilled in comprehending a problem and coming up with quick solutions. Skills: RTL design, computer architecture, logic design, digital circuit design, full custom ASIC design, FPGA synthesis. Excellent communication skills: Oral, Written and Presentation. Good teamwork ability. Languages: Verilog HDL, VHDL, C, C++, Shell scripting, Perl scripting, MIPS AssemblyApplications: Verdi, NCSim, Synopsys DC, Encounter, Primetime, Virtuoso, Xilinx ISE, Chiscope Pro
Experience
Principal Design Engineer
Jun 2019 — Present
Education
University of Southern California
Master of Science (MS), Electrical Engineering
2013 — 2014
Sri Jayachamarajendra College of Engineering
Bachelor of Engineering (BE), Electrical, Electronics and Communications Engineering
2009 — 2013
Skills
- Ltspice
- Xilinx
- Microcontrollers
- C++
- Sensors
- Opencv
- Mips
- Ic
- Vlsi Cad
- Microprocessors
- Atmel Avr
- Java
- C++ Language
- Express Pcb
- Xilinx Ise
- Modelsim
- Vlsi
- Vhdl
- Shell Scripting
- Logic Design
- Verilog
- Pspice
- Perl
- Ccna
- Programming
- Computer Architecture
- Leonardo Spectrum
- Ic Station
- Labview
- Eclipse
- Digital Electronics
- Matlab
- Cadence Virtuoso
- Fpga
- X86 Assembly
- Logic Synthesis
- Scilab
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