Viresh Hingarh
Vice President , ASIC Implemention
- Role
- Vice President, Asic Implementation at Eximietas Design
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
About Viresh Hingarh
20+ years of experience in physical design and layout using Cadence SoC Encounter/Innovus, ICC/ICC2 and Primetime/SI for STA. Extensive experience in synthesis, floorplanning, placement, CTS, routing, DRC/LVS and final timing signoff. Includes hierarchical and flat top level integration/design and hierarchical block level design.Achieved a number of successful tapeouts in 5nm, 7nm, 16nm, 28nm, 40nm, 65nm, 90nm, and 130nm using foundries like TSMC, Samsung, Chartered, TI and ST Microelectronics.Experience in high-end, high density designs such as graphics processors (50M+ gates) and multiple complex networking processors (10M+ gates)Experience in CAD, methodology and flow development for multiple designs and multiple technologies.Experience in leading teams of engineers for complete P&R, final signoff and tapeout.
Experience
Vice President, Asic Implementation
Jan 2025 — Present · US
Education
California Polytechnic State University-San Luis Obispo
Bachelor of Science (B.S.), Computer Engineering
1997 — 2001
Santa Clara University
Masters, Electrical Engineering
2002 — 2004
Skills
- System on a Chip (Soc)
- Soc
- Asic
- Semiconductors
- Logic Synthesis
- Application-Specific Integrated Circuits (Asic)
- Magma
- Place & Route
- Physical Design
- Static Timing Analysis
- Processors
- Vlsi
- Routing
- Floorplanning
- P&R
- Ic
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