Vetri Ayyavu
Senior Principal Engineer Lead Chip Architect - Intel Ipu @Intel
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WORK HISTORY
Senior Principal Engineer Lead Chip Architect - Intel Ipu @Intel
Defining Intel\'s next generation IPU System-on-Chip Architecture -(Infrastructure Processing Unit - aka Smart-NIC, developments for the cloud data center)
EDUCATION
Government Polytechnic
Diploma , Electronics & Communication Engineering
Institution Engineers (India), Calcutta
AMIE, Bachelors Engineering , Electronics & Communication Engineering
Government College of Technology, Coimbatore, India
Masters Engineering, MS, Applied Electronics
ABOUT VETRI AYYAVU
System-on-Chip (SoC) architect specialized in high performance high core count compute system architecture definition for Cloud Data center, Server/HPC, Edge, Networking, Storage application specific Chips and most recently Edge AI. Specialized expertise in ARM Architecture CPUs such as Neoverse V-series, N-series & Cortex-A, R&M families of processors and associated System IPs, Coherent Mesh Network Interconnect (CMN), Interrupt Architecture (GIC), System Memory Management (SMMU), Debug (CoreSight), etc,RISC-V CPU architecture & AI accelerators are the new additions to the list.Experience in latest process technology nodes, TSMC 5nm, 7nm, 16FF, 28nm and current cutting-edge nodes in both TSMC & Intel. Multi-Chiplet systems and its Packaging technologies, 2D, 2.5D & 3DHigh-speed protocol/IO experiences PCIe Gen6/5/4 (latest), CCIX (chip-to-chip interconnect protocol), CXL, UCIe and other high technologies such as SAS, SATA, Interlaken, Ethernet.Key enterprise SoC & IP developments: Intel IPU (Smart-NIC), ARM based datacenter SoCs, Enterprise-SSD, SAS, SATA, PCIe/NVMe, Storage RAID controllers, Network Packet Processors, LTE, WCDMA, etc, Industry standard protocol specification development participation: First-gen SATA, SAS (Serial Attached SCSI), PCIe Gen1/2 & USB3.0 Expert experience in end-to-end Front-end chip developments, Micro-Architecture, RTL design/coding, Verification (DV), Synthesis, Timing Closure (RTL to GDSII) & FPGA prototyping (Altera/Xillinx), Silicon ValidationHands on management experience in leading larger Hardware development teams that includes system/SoC architecture, ASIC/FPGA, Hardware system board & Embedded SW developments. 11 US Patents in SAS, SATA & SSD Technologies.
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