Venu Pakalapaty
Director, Engineering @Qualcomm
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WORK HISTORY
Director, Engineering @Qualcomm
Bengaluru, IN
Modem (5G/4G, IOT) HW leadGNSS/Navigation HW LeadWLAN: Design-Verification, Algorithm-Modeling, Virtual PlatformsIP/Core development with focus on datapath designs. Delivery to Snapdragon SOCs
EDUCATION
Indian Institute of Science (IISc)
Masters of Engineering
ABOUT VENU PAKALAPATY
Demonstrated strong track record of technical leadership, Domain skills, strong execution over the past 23 years, with a good ~19 years’ of that experience coming from Qualcomm.Currently Leading the AI Processors HW group with focus on IP and Sub-System development spanning across Design, DV, Synth, STA, Power and VI job-functions. Also drive the Architecture & HW development on Compression IPs. Design and Development of Neural Processing enginess (HW accelerators) with KPIs such as low-latency, low-power and high performance cateringt to XR, Auto, Compute and Mobile products.Held different roles that includes HW Org lead, Technical lead, Project lead & Individual contributors. Had the opportunity to lead HW IP development on key technologies like Neural / AI Processors, Cellular Modem(5G/4G/3G), GNSS/Navigation, WLAN and IP Packet accelerators and IP delivery to SOC chips (Snapdragon processors). Generating novel ideas, proof-of-concepts, inculating Innovation in the team with hope of converting them into potential IDF filingsWorked in a global organisation setup with teams spanned across multiple locations (US, Canada, China, Israel India) demonstrated strong collaboration with cross-functional teams & Geo-leads. Demonstrated the ability to build teams from scratch. Exhibited strong appetite for technical learning by taking up big-ticket initiatives for KPIs improvements like Chip Area/Power/Performance aiding AUC reduction. Tester Time reductions initiatives that saved NRE significantly. Contributed to about 50 Tapeouts (Premium, High and Value Tier platforms), on SOCs that were commercially successful in the Smartphones, Tablet and Access point, Tab/Laptop, Virtual/Augmented reality product lines.Low-power/High-speed (~2 GHz, 3 nm tech nodes) Digital design realisation and ASIC first pass success. Design of datapath/contol paths in Wireless & Neural Signal processors that includes Arch/Mcro-arch, verification, validation, modelling, implementation.Lead Design-Archicture, Design-Implementation, Verification, Algorithm Modeling, Virtual Prototype (ESL). Contributed to new methodologies/flow/processes with hope of NRE reduction or Quality improvement including TTM
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