Venkat Vishal Vusirikala
Product Engineer at Cadence Design Systems | EMIR & PDN Analysis | SoC Power Integrity Signoff | ASU Alumni | PESU
- Role
- Product Engineer Ii at Cadence
- Location
- Austin, TX, US
- LinkedIn followers
- 500 followers
About Venkat Vishal Vusirikala
I hold a Master’s degree in Electrical Engineering from Arizona State University. Currently, I am a Product Engineer at Cadence Design Systems, specializing in power noise reliability analysis and power integrity for digital designs and I work closely with R&D to develop advanced methodologies like AI-driven IR mitigation and 3DIC analysis while supporting strategic customers with technical solutions.With expertise in digital logic design, CMOS design, and PDN analysis, I focus on optimizing power integrity sign-off and debugging complex architectures. Proficient in scripting with TCL and Python, I strive to enhance semiconductor design efficiency and reliability.
Experience
Product Engineer Ii
Mar 2025 — Present · Austin, TX, US
Education
PES University
Bachelor of Technology - BTech
2016 — 2020
Arizona State University
Master of Science - MS
2022 — 2024
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