Venkateshwara P Chandrasekaran

About Venkateshwara P Chandrasekaran

Motivated quality assurance professional with a solid understanding of hardware design and a desire to contribute to a company’s objective while expanding personal knowledge and abilities. Well-founded knowledge of ASIC design flow, RTL design, Micro-architecture definition and FPGA based system design. Experienced in SOC level verification based on System Verilog UVM and constrained driven verification environment, as well as strong EDA tool skills. Strong analytical ability, problem solving and communication skills. Ability to work independently, also a good team player. Multitasking highly motivated and results driven. Always on the lookout for challenging opportunities that can further my learning/understanding of the tech world.Specialities: RTL design in Verilog in a SOC and ASIC environment;Good knowledge of scripting languages like PERL, Shell and TCL.Well versed in C++, System Verilog, Python, Make and Assembly Language.Experience with UNIX/ Linux Environment.Excellent background in tools like Cadence Virtuoso layout and Schematic suite, Xilinx ISE, Synopsys Design Compiler for RTL logic synthesis, Synopsis prime time and Synopsys VCS. Rich understanding and experience of UVM verification methodology.

Experience

1. Staff Design Verification Engineer

   Qualcomm

   Nov 2025 — Present · Santa Clara, CA, US

Education

• University at Buffalo School of Engineering and Applied Sciences

  Master's degree, Electrical, Electronics and Communications Engineering

  2016

• JGVV MHSS CHENNAI

  High school, Computer Science

  1997 — 2012

• Anna University Chennai

  Bachelor of Engineering (B.E.), Electrical, Electronics and Communications Engineering

  2012 — 2016

Skills

• Pspice
• Xilinx Ise
• Design
• Object-Oriented Programming (Oop)
• Application-Specific Integrated Circuits (Asic)
• Leadership
• Computer Architecture
• Customer Service
• Perl
• Linux
• Very-Large-Scale Integration (Vlsi)
• C
• Programming
• Proteases
• System Verilog
• Management
• Verification and Validation (V&V)
• Microsoft Word
• Cadence Virtuoso
• C++
• Microsoft Powerpoint
• Microsoft Office
• Microsoft Excel
• Matlab