Venkatesh Gangal
SoC PD Engineer at Apple
- Role
- Soc Pd Engineer at Apple
- Location
- Austin, TX, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Soc Pd Engineer
May 2024 — Present · Austin, TX, US
Education
Illinois Institute of Technology Chicago
Master’s Degree, Computer Engineering
2015 — 2017
Skills
- Cadence Spectre
- Perl
- Eda
- Microsoft Office
- Vlsi
- Functional Verification
- Field-Programmable Gate Arrays (Fpga)
- Cadence Encounter
- Matlab
- Mixed Signal
- Dft
- Modelsim
- Physical Design
- Synopsys Primetime
- Verilog
- Pspice
- Vhdl
- Simulations
- Ic Layout
- Application-Specific Integrated Circuits (Asic)
- Physical Verification
- Xilinx
- Systemverilog
- Very-Large-Scale Integration (Vlsi)
- C++
- Logic Design
- Rtl Verification
- Microsoft Excel
- Microsoft Word
- Electronics
- Arm Architecture
- Layout Versus Schematic (Lvs)
- Logic Synthesis
- Design Rule Checking (Drc)
- System on a Chip (Soc)
- Static Timing Analysis
- Cadence Virtuoso Layout Editor
- Rtl Design
- C
- Cadence
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.