Venkatesh Pemmanaboyina

WORK HISTORY

EDUCATION

SKILLS

ABOUT VENKATESH PEMMANABOYINA

With strong expertise in logic library characterization and cell modeling in VLSI standard cells, I lead a team responsible for characterizing standard cells across multiple technology libraries. My experience includes working on various custom complex cells, ensuring high-accuracy modeling for advanced semiconductor designs.We develop NLDM/NLPM, CCS, CCS noise, and ECSM liberty models, ensuring precise timing and power characterization. To accurately model process variation, we create hold margin, LVF (Liberty Variation Format), AOCV (Advanced On-Chip Variation), POCV (Parametric On-Chip Variation), and spatial OCV models, improving design robustness under different manufacturing conditions.Additionally, we develop MIS (Multi-Input Switching) views, which help in considering multi-input switching scenarios in circuit design, leading to better timing and noise analysis. We also build aging library models, crucial for automotive libraries where reliability over extended lifetimes is a key requirement.To address electromigration (EM) concerns, we develop electromigration models that incorporate EM toggle rates or frequency-based EM max cap limits, ensuring reliable current density management in advanced technology nodes.I also have theoretical knowledge in areas such as synthesis, physical design, STA, signal and power integrity, electromigration, and dynamic IR drop analysis, which enhances my ability to understand and optimize the broader VLSI design flow.